Learn chip verification, one rising edge at a time

PosEdge
APB LabAn interactive AMBA APB protocol tutorial, from waveforms to SVA and UVM

APB is the simplest bus in the AMBA family. Three states, two cycles per transfer, five rules. You can learn the whole protocol in under an hour and be ready to verify it the same day.

  • 3states
  • 2cycles per transfer
  • 5rules to remember
  • 45minutes to learn the protocol
START HERE

Your roadmap

Four stages, in order. Stages 1 and 2 teach the whole protocol. Stages 3 and 4 make you verification-ready. Every chapter ends with one line to remember and a button to the next one, so you never have to wonder where to go.

  • Hover or tap a waveform to read that clock cycle in plain English.
  • Click to pin a cycle, then use ← → to step one clock at a time.
  • In the lab, choose a scenario first. Each scenario is one waveform. Then apply assertions and constraints to it with one click.
  • Prefer to listen? Press Voice guide at the bottom right, or Listen next to any chapter title, for a short spoken guide to that section.
  • Progress saves in this browser, so you can stop and come back later.
01 · BASICS

APB in three lines

Start with the three signals that run every transfer. Then see where APB sits in a chip and why it is built so simply.

PSEL says who.The requester selects one completer and puts the address on the bus.

PENABLE says now.One cycle later, it starts the access.

PREADY says done.The completer finishes when it is ready.

At the clock edge where all three are high, the transfer happens. This page calls it the triple-high edge. That one sentence is most of APB.

Try it now · move across this waveform: a write with one wait state, then a read

Where APB sits

CPU requester AXI / AHB high-speed fabric APB bridge APB requester PSEL1PSEL2PSEL3PSEL4 UARTGPIOTimerWatchdog shared PADDR · PWRITE · PENABLE · PWDATA PRDATA · PREADY · PSLVERR muxed back by PSEL

A CPU talks to memory over a fast, pipelined bus such as AXI or AHB. Peripheral registers do not need that speed. An APB bridge converts each fast-bus access into one APB transfer and acts as the only requester on the APB side. Each peripheral is a completer with its own select line, PSELx. Address, write data and control wires are shared.

AMBA 5 documents use Requester and Completer. Older documents and most existing RTL say master and slave. They mean the same roles.

Every transfer has two phases. In SETUP the requester raises PSELx and puts address, direction and write data on the bus. One cycle later it raises PENABLE for ACCESS. From APB3 onward the completer can stretch ACCESS by holding PREADY low. The transfer completes at the rising edge where PSEL, PENABLE and PREADY are all high.

That is the whole protocol. The rest is detail about what must stay stable, what is sampled when, and what each later version added.

Why it's cheapNo pipelining, no bursts, no IDs, no outstanding transactions, one requester. A completer can be a register bank plus three gates of decode logic.
Why it's slowEach transfer takes at least two cycles, so peak throughput is one transfer every two cycles. Wait states lower that further.
TimingEverything is synchronous to the rising edge of PCLK. In these waveforms, cycle n is sampled at edge Tn+1.
02 · SIGNALS

Every signal, and when it arrived

Pick a version to see which signals exist in it. Rows that are new in that version are highlighted.

SignalWidthDriven bySinceWhat it doesWhat to verify
PCLK1Clock sourceAPB2Clock. All signals are timed against its rising edge.No logic on the falling edge; check behaviour when the clock is gated.
PRESETn1System resetAPB2Active-low reset, normally the system bus reset.PSEL and PENABLE low during reset; reset in the middle of a transfer.
PADDR≤ 32RequesterAPB2Byte address of the access.Stable from SETUP to completion; boundary, unmapped and unaligned addresses.
PSELx1 eachRequester (decoder)APB2One select per completer. High for the whole transfer.At most one high (one-hot-zero); never dropped during a wait state.
PENABLE1RequesterAPB2Low in SETUP, high in ACCESS. Marks the second phase.Never high without PSEL; rises only after one SETUP cycle; drops after every completion.
PWRITE1RequesterAPB21 = write, 0 = read.Stable during the transfer; read-after-write to the same address.
PWDATA8 · 16 · 32RequesterAPB2Write data.Valid and stable for every cycle of a write.
PRDATA8 · 16 · 32CompleterAPB2Read data, sampled only in the completing cycle.No X at completion; a completer that is not selected must not corrupt the bridge's read mux.
PREADY1CompleterAPB3Low extends ACCESS with wait states; high completes it.Ignored in SETUP; tie-high completers; long stalls and timeouts.
PSLVERR1CompleterAPB3Error response for the transfer.Only valid when PSEL, PENABLE and PREADY are high; scoreboard handling on read and write.
PPROT3RequesterAPB4[0] privileged, [1] non-secure, [2] instruction. Each bit means that when it is 1.All 8 values covered; secure-only or privileged-only registers reject the other kind.
PSTRBDATA/8RequesterAPB4Byte-lane write strobes. PSTRB[n] enables PWDATA[8n+7:8n].All zeros on reads; sparse and empty strobes on writes; interop with APB3 completers.
PWAKEUP1RequesterAPB5Signals activity so a power-managed completer can wake before the transfer.Driven from a register (glitch-free); asserted before or with PSEL; held until completion.
PAUSERuserRequesterAPB5User-defined request attribute.Same stability rule as PADDR.
PWUSERuserRequesterAPB5User-defined write-data attribute.Same stability rule as PWDATA.
PRUSERuserCompleterAPB5User-defined read-data attribute.Sampled with PRDATA.
PBUSERuserCompleterAPB5User-defined response attribute.Sampled with PSLVERR.
PNSE1RequesterAPB5 · RMEAdded with Arm's Realm Management Extension. With PPROT[1] it selects one of four physical address spaces: Secure, Non-secure, Root, Realm.All four address spaces covered; access-filter checks per space.
*CHKvariesBothAPB5Optional interface protection: PADDRCHK, PCTRLCHK, PSELxCHK, PENABLECHK, PWDATACHK, PSTRBCHK, PREADYCHK, PRDATACHK, PSLVERRCHK, and more. Odd parity per byte or per signal group.Inject single-bit errors on each protected signal and check that the receiver flags them.
03 · STATE MACHINE

Three states drive everything

Queue a few transfers, choose whether the completer is ready, and clock the bus one edge at a time. The highlighted arrow is the transition the next edge will take, and the waveform below grows cycle by cycle.

no transfer transfer requestedPSELx = 1 alwaysPENABLE = 1 PREADY = 1and transfer PREADY = 1no transfer PREADY = 0 (wait) IDLEPSEL=0 SETUPPSEL=1 EN=0 ACCESSPSEL=1 EN=1
Pending transfers
Transition log

    Reading the diagram

    • IDLE is the default. The bus stays here while nothing is requested.
    • SETUP lasts exactly one cycle, always. There is no condition on the SETUP → ACCESS arc.
    • ACCESS repeats while PREADY is low. Each repeat is a wait state.
    • From a completing ACCESS the bus goes straight to SETUP if another transfer is pending. That is a back-to-back transfer: PSEL stays high and only PENABLE drops.

    Try it: queue two transfers, untick Completer ready for two clocks during ACCESS, then tick it again.

    CHECKPOINT

    Three questions, then you know APB

    If you can answer these, you understand the core of the protocol. Everything after this adds detail, not new ideas.

    04 · WAVEFORM LAB

    Choose, watch, apply

    Choose a scenario, then watch its waveform. Everything you apply, whether an assertion, a bug or random stimulus, is picked right above the waveform and shows up on it, with the explanation right below it.

    Choose a scenario to learn

    Each scenario is one waveform that teaches one idea. Pick one here and the waveform in step 2 changes to it. Start at the top left and work through them in order.

    Watch it, then apply

    Press Play or move across the waveform. Then use the three menus right above it. What you pick is marked on the waveform and explained under it.

    signals the assertion looks ata check✕a failed checkchanged by the bug, constraint or editwait statetriple-high edge

    Go deeper

    Write and score your own assertion, set several constraints at once and watch coverage fill, browse all the bugs, or edit the waveform by hand. Each one shows its result on the waveform in step 2.

    Write your own assertion from three parts. It is applied to the waveform above as My assertion, and the score below tests it against every legal scenario and every bug.

    Your assertion
    Challenges · write an assertion that…
      Build your own scenario · edit the transfer table
      05 · VERSIONS

      APB2 to APB5, one waveform each

      Each version kept the two-phase transfer and added signals around it. Each card shows one scenario for that version; press Open in lab, then choose other scenarios in step 1 of the lab to see more waveforms for the same version.

      APB2AMBA 2 · 1999

      Fixed two-cycle transfer.

      APB3AMBA 3 · 2003–04

      Wait states and errors.

      APB4AMBA 4 · 2010

      Protection and byte strobes.

      APB5AMBA 5 · 2021 →

      Wake-up, user signals, parity.

      APB2

      AMBA 2 APB
      Signals: PCLKPRESETnPSELxPENABLEPADDRPWRITEPWDATAPRDATA

      There is no PREADY, so every transfer is exactly one SETUP cycle and one ACCESS cycle. A completer that is slow has no way to say so: it must answer within that ACCESS cycle. There is no error signal either.

      APB3

      AMBA 3 APB v1.0
      Adds: PREADYPSLVERR

      The completer holds PREADY low to insert wait states, and drives PSLVERR high in the completing cycle to report an error. An APB2 completer works on an APB3 bus with PREADY tied high and PSLVERR tied low. The waveform shows a write with one wait state that fails, then a read that fails.

      APB4

      AMBA APB v2.0
      Adds: PPROT[2:0]PSTRB[DATA/8-1:0]

      PPROT carries privileged / non-secure / instruction attributes so a completer can filter accesses. PSTRB allows sparse writes: only byte lanes with a strobe bit set are updated, and PSTRB must be all zeros on reads. Here a write updates only the low two bytes, then the read returns the merged word.

      Interop trapAn APB3 completer has no PSTRB input. If an APB4 requester sends a partial write to it, the completer writes the full word and corrupts the bytes that should have been left alone. The interconnect must block, error, or emulate those writes.

      APB5

      AMBA 5 APB, Issue D onward
      Adds: PWAKEUPPAUSERPWUSERPRUSERPBUSER*CHK parityPNSE (RME)

      PWAKEUP tells a clock-gated or power-gated completer that activity is coming, so it can wake before PSEL. User signals carry implementation-defined sideband data with the same timing as the signal they accompany. The optional check signals add odd parity for functional-safety designs. The waveform shows PWAKEUP leading PSEL by two cycles.

      Feature matrix

      FeatureAPB2APB3APB4APB5
      Two-phase SETUP / ACCESS transfer✓✓✓✓
      Wait states (PREADY)–✓✓✓
      Error response (PSLVERR)–✓✓✓
      Protection attributes (PPROT)––✓✓
      Byte strobes (PSTRB)––✓✓
      Wake-up hint (PWAKEUP)–––✓
      User sideband signals–––✓
      Interface parity protection–––✓ optional
      Realm Management (PNSE)–––✓ later issue
      Minimum cycles per transfer2222
      06 · PROTOCOL RULES

      Five rules cover almost everything

      Learn these five. Each one is checked by an assertion, and each card has a button that loads a bug breaking it into the lab, so you can watch the assertion fire.

      1

      One beat of SETUP

      PSEL rises with PENABLE low for exactly one cycle. Then ACCESS, always.

      a_setup_to_accessa_rose_en_after_setup

      2

      Freeze till READY

      From SETUP to the triple-high edge, nothing the requester drives may change.

      a_wait_holda_stable_ctrla_stable_wdata

      3

      ENABLE needs SELECT

      PENABLE is never high on its own. No PSEL, no PENABLE.

      a_en_needs_sel

      4

      Drop ENABLE after

      After every completion PENABLE goes low, even when PSEL stays high for the next transfer.

      a_en_drop

      5

      Sample at triple-high

      PRDATA and PSLVERR only count at the edge where PSEL, PENABLE and PREADY are all high.

      a_no_x_rdataa_err_only_on_done

      Every assertion the lab runs

      The same names as the SVA checker in chapter 09. Errors break the protocol; warnings flag recommendations and testbench policy.

      AssertionGroupWhat it checksWhen · thenLevel
      RecommendedAfter a transfer, keep PADDR and PWRITE at their last values until the next transfer. It is not required, but it avoids needless toggling on a wide shared bus.
      Don't carePREADY in SETUP, PRDATA outside the completing read cycle, and PWDATA during reads carry no meaning. A checker that flags them is wrong.
      07 · CORNER CASES

      Where APB designs actually break

      Every item here has caught a real bug somewhere. Each card says why it matters and how to hit it in a testbench. Several are loadable presets in the lab.

      Timing and flow

      Zero wait states

      The fastest case: SETUP then one ACCESS. Completers that need a cycle to decode often have bugs only here.

      Hit itForce or tie PREADY high; weight wait_cycles == 0 heavily.

      Long stalls

      A completer holds PREADY low for many cycles. APB has no timeout, so the bridge or the CPU hangs unless something watches.

      Hit itRandomise 0 to 16+ waits; add a bounded-completion assertion and a bridge watchdog test.

      PREADY high during SETUP

      Legal, and must be ignored. A completer that defaults PREADY high is common. A requester that completes on it is broken.

      Hit itCompleter model option that drives PREADY=1 when idle. Lab preset: PREADY high during SETUP.

      Back-to-back, same completer

      PSEL never falls; only PENABLE pulses low. Completers that use PSEL's falling edge to finish an operation miss the second transfer.

      Hit itidle_cycles == 0 sequences; cover done ##1 setup.

      Back-to-back, different completers

      PSEL1 falls in the same cycle PSEL2 rises. The read mux in the bridge must switch cleanly.

      Hit itAlternate target regions with zero idle cycles. Lab preset: two peripherals.

      Read immediately after write

      Back-to-back read of the address just written. Exposes write pipelines that update a cycle late.

      Hit itDirected W→R pairs to the same address with 0 waits.

      Responses

      PSLVERR on a write

      The register may or may not have been updated. A scoreboard that assumes either way will produce false failures.

      Hit itError-injecting completer model; scoreboard marks the location unknown.

      PSLVERR on a read

      PRDATA is not guaranteed valid. The requester must not forward it as good data.

      Hit itReturn garbage with PSLVERR=1 and check the bridge's response to the fast bus.

      Error after wait states

      PSLVERR is only meaningful on the final cycle. A requester sampling it on every ACCESS cycle sees noise.

      Hit itCross wait_cycles with slverr in coverage.

      Unmapped address

      An address inside the APB region but outside any completer. Something must still answer, or the bus hangs.

      Hit it10% of addresses outside the map; expect a default completer with PSLVERR or read-as-zero, per your design spec.

      Data and strobes

      Write with PSTRB = 0000

      Legal in APB4. No bytes change. Completers that ignore strobes write anyway.

      Hit itKeep 0 in the strobe distribution; check the register is unchanged.

      Sparse strobes

      Single bytes, half-words and patterns like 0101. Byte-enable logic often handles 1111 and nothing else.

      Hit itCoverpoint bins for each single lane, both halves, and others.

      Partial write to an APB3 completer

      No PSTRB input, so it writes the whole word. See the APB4 interop trap.

      Hit itSystem-level test through the real interconnect, not just block level.

      Unaligned address

      PADDR low bits not zero. Behaviour is design-specific: aligned-down, error, or ignored.

      Hit itTurn off the alignment constraint in one test; check against the register spec.

      Reset, power, protection

      Reset in the middle of a transfer

      Both sides must return to IDLE. The requester must not complete the old transfer after reset deasserts.

      Hit itAssert PRESETn at a random cycle during ACCESS; restart traffic.

      First transfer after reset

      The very first cycle after release. Exposes state that is not initialised by reset.

      Hit itLab preset: Reset, then the first transfer.

      Wake from clock gating (APB5)

      A transfer starts right after PWAKEUP rises. The completer's clock must be running by SETUP.

      Hit itVary PWAKEUP lead from 0 to several cycles.

      Protection mismatch

      Non-secure access to a secure register, unprivileged access to a privileged one. Expect PSLVERR or read-as-zero, write-ignored.

      Hit itCross PPROT with register address in coverage.

      Parity error injection (APB5)

      Flip one bit on a protected signal or its check bit. The receiver must flag it.

      Hit itError-injection callbacks in driver and completer model.

      08 · COMMON BUGS

      Bugs you will meet, and what catches them

      Design bugs first, then testbench bugs. Testbench bugs are worth as much attention: they either hide design bugs or waste days on false failures.

      In the design

      Bug

      Write happens in SETUP

      Completer decodes PSEL && PWRITE without PENABLE.
      SymptomRegister updates a cycle early. With wait states, a FIFO push or write-to-clear fires on every cycle of the transfer.
      Caught byScoreboard with randomised waits; FIFO level checks. Fix: qualify with PSEL && PENABLE && PREADY.
      Bug

      Read side effect repeats

      Read-to-clear status or FIFO pop on every ACCESS cycle, not just the completing one.
      SymptomLost FIFO entries or cleared flags whenever the read has wait states.
      Caught byReads with wait states to side-effect registers, compared against a reference model.
      Bug

      Wait counter not reset at completion

      Counter only resets on PSEL low.
      SymptomBack-to-back transfers get the wrong number of wait states, so data is sampled early.
      Caught byBack-to-back sequences plus a monitor that records wait_cycles.
      Bug

      PSTRB ignored

      Completer writes all four bytes regardless of strobes.
      SymptomNeighbouring bytes corrupted by partial writes.
      Caught byStrobe coverage plus a byte-accurate register model.
      Bug

      PRDATA driven when not selected

      Completer drives its register value onto PRDATA at all times.
      SymptomBridges that OR the PRDATA of all completers return corrupted read data.
      Caught byReads to one completer while another holds non-zero data; a check that PRDATA is zero when PSEL is low, if the design spec requires it.
      Bug

      Bridge changes PADDR in a wait state

      Bridge forwards the next fast-bus address while APB is still waiting.
      SymptomThe completer acts on the wrong register.
      Caught bya_stable_ctrl, with completers that insert waits.
      Bug

      Incomplete address decode

      Completer compares only low address bits.
      SymptomRegisters alias across the region; writes to one offset change another.
      Caught byWalking-ones address test and aliasing checks in the register model.

      In the testbench

      Bug

      Monitor samples on PENABLE

      Transaction captured when PSEL and PENABLE are high, ignoring PREADY.
      SymptomDuplicate or garbage transactions for every wait state.
      FixCapture only when PSEL, PENABLE and PREADY are all high.
      Bug

      Driver waits a fixed cycle

      Driver drops PSEL after one ACCESS cycle.
      SymptomPasses against zero-wait completers, breaks the protocol against any completer with waits.
      FixLoop on PREADY. Exercise E8 walks through it.
      Bug

      Race with the DUT

      Driver uses blocking assignments at posedge without a clocking block.
      SymptomResults change with simulator or event ordering.
      FixDrive and sample through clocking blocks.
      Bug

      Comparing PRDATA on errors

      Scoreboard checks read data even when PSLVERR is high.
      SymptomFalse failures on every error test.
      FixSkip or special-case the comparison on errors.
      Bug

      Illegal stimulus

      Sequence item lacks dir == READ -> strb == 0.
      SymptomChecker fires on stimulus, and the team weakens the checker to make it pass.
      FixConstrain the item. Never relax a correct checker to suit a wrong testbench.
      Bug

      Assertions active in reset

      No disable iff.
      SymptomA flood of failures at time zero that people learn to ignore.
      FixDefault disable on reset; a separate reset-state check.
      09 · ASSERTIONS

      A complete SVA protocol checker

      Bind this to any APB completer interface. It holds every assertion the lab runs (chapter 06 lists them), and the cover properties tell you whether your stimulus reached the interesting cases. Want to see one fire? Each golden rule in chapter 06 has a See it break button, and the lab's Build your own tab lets you write and score your own.

      Gotchas that cost interview points

      • |-> checks the consequent in the same cycle; |=> checks it one cycle later. "SETUP is followed by ACCESS" needs |=>.
      • $stable(x) compares the current sample to the previous one. Put it after |=> with SETUP or a wait state as the antecedent, so it checks each step of the transfer.
      • $past and $rose look one sampled clock back. Right after reset release that value may come from the reset period.
      • The reset check needs its own disable iff (1'b0), otherwise the default disable switches it off exactly when it should run.

      Why some checks are warnings

      a_err_only_on_done encodes a recommendation: the specification asks completers to drive PSLVERR low outside completion but does not require it. Making it an error would fail legal designs.

      a_max_wait is a liveness proxy. APB allows unbounded wait states, so the bound is testbench policy. In formal, prefer a real liveness property with fairness assumptions on the completer.

      10 · CONSTRAINTS

      Stimulus that is legal by construction

      The sequence item carries both requester-side fields (address, data, strobes, protection, idle gap) and completer-side fields (wait states, error) so one item drives a requester agent or a reactive completer agent.

      Design choices worth defending

      • Constrain protocol rules, weight corner cases. c_strb_read is a hard rule. Everything else is a distribution, so legal corners like strb == 0 still appear.
      • := vs :/. := gives the weight to every value in a range; :/ splits it across the range. [1:3] :/ 35 means 35 in total, not 105.
      • solve dir before strb keeps the direction split near 50/50. Without it, the many strobe values on writes pull the solver toward writes.
      • Turn constraints off by name with constraint_mode(0) for one corner test, rather than weakening the base class.
      • Redeclaring a constraint with the same name in a subclass replaces the parent's version. That is how a test-specific item changes the address range.
      11 · COVERAGE

      Prove the corners were reached

      Transaction-level coverage from the monitor, plus the signal-level cover properties in chapter 09. Together they close the corner cases from chapter 07.

      Coverage plan

      FeatureCovered byGoal
      Read and write to every registercp_addr.regs × cp_dir100%
      Wait states 0, 1, few, many, max for reads and writesx_dir_wait100%
      Error on read and write, with and without waitsx_dir_err, x_err_wait, c_err_after_wt100%
      Back-to-back in all four direction pairsx_b2b_seq, c_back_to_back100%
      Every strobe class, including 0000cp_strb, c_strb_zero100%
      Every PPROT value on every registerx_prot_reg100%
      PREADY high during SETUPc_ready_setuphit ≥ 1
      Region boundary (last word)cp_addr.lasthit ≥ 1
      Watch outSample coverage in the monitor's write() after the transaction is complete. Sampling when the item leaves the sequencer records what you asked for, not what the DUT did; wait states and errors chosen by the completer would never show up.
      12 · REFERENCE TESTBENCH

      RTL, interface, driver and monitor

      A small completer to verify and the minimum UVM pieces to drive it. Each one encodes a rule from this page; the comments say which.

      Next step · full UVM environment

      Verify an APB RAM with UVM, end to end

      The pieces above are the minimum. This playground is a complete UVM testbench for an APB RAM: an agent with a driver, a monitor and a sequencer, a scoreboard, functional coverage, and two tests. Open it, read how each piece maps to the waveforms on this page, then click Run.

      Open on EDA Playground ↗
      Testbench

      apb_ifapb_typesapb_seq_itemapb_sequenceapb_driverapb_monitorapb_agentapb_sbapb_coverageapb_envapb_pkgtestbench

      Tests
      • apb_random_access_test constrained-random reads and writes, checked by the scoreboard
      • apb_access_reserved_addr_test accesses to reserved addresses, where PSLVERR is expected

      Viewing the code needs no account. To run it, log in to EDA Playground with a free account, and keep a UVM version and simulator selected on the left.

      13 · DRAW IT

      Draw the waveform from memory

      Interviewers ask you to draw APB timing on a whiteboard. Practise it here: read the task, click the cells to draw each signal, then check. Grey hatched cells are don't-care, because APB never samples that signal in that cycle.

      highlowdon't carewrong after checking
      14 · EXERCISES

      Find it, write it, fix it

      Three kinds of practice. The bug hunt asks where a waveform breaks. The lab tasks send you back to the lab. The written exercises ask you to write the SVA, constraints and coverage yourself.

      Lab tasks

      1. In the lab, choose the scenario Write with waits. Switch to Edit by hand, change PADDR in the second wait cycle, then press Apply it to the waveform next to a_stable_ctrl and read where it checked and where it failed.
      2. Build write → read → write to the same address with waits 0, 2, 1 and no idle cycles between them. Predict the total cycle count before you look. (Each transfer is 2 + waits.)
      3. In APB4, write 0xAABBCCDD with PSTRB = 0101 to a register holding 0x11223344, then read it back. What value should the read return? Set PRDATA in the table to match.
      4. Using the Insert a bug menu, catch all 14 bugs. For each one, say out loud why the two wrong answers still pass.
      5. In the Random stimulus menu above the waveform, choose Without c_strb_read and find the outlined cell. Then choose Without c_aligned: why does no assertion fire?
      6. Reach 100% coverage on APB4 with as few runs as you can. Which bins were hardest, and which constraint would you change to hit them faster?

      Written exercises

      E1

      Assert that PWDATA is stable during a write

      Basic

      Write a property that fails if PWDATA changes at any point between SETUP and the completing cycle of a write. Do not use the helper wires from chapter 09.

      Hint

      The antecedent is "SETUP or wait state, and it is a write". Use |=> and $stable.

      Solution
      E2

      Bounded completion

      Basic

      Assert that every transfer completes within 8 cycles of its SETUP cycle. Then explain why this is a testbench policy and not an APB rule.

      Solution

      The earliest completion is one cycle after SETUP, hence ##[1:8]. APB places no limit on wait states, so this bound comes from your system requirements (for example, the CPU's bus timeout). In formal verification, a fixed bound can also hide a real deadlock beyond it.

      E3

      Read-after-write constraint

      Intermediate

      Write constraints for a block of six transfers where every read targets an address that some earlier transfer in the block wrote.

      Hint

      The first transfer must be a write. Array reduction with item.index can express "exists an earlier j".

      Solution
      E4

      Unmapped addresses and a strobe corner test

      Intermediate

      Extend apb_txn so that about 1 in 10 addresses falls outside the mapped region, and so that write strobes are never zero, except in one directed corner test that writes with strb == 0.

      Solution
      E5

      Per-register coverage

      Intermediate

      Write a covergroup that proves each of 16 registers was both read and written, each with and without an error response. How many cross bins does it have?

      Solution
      E6

      Debug this completer

      Intermediate

      This completer passed all zero-wait tests. With 2 wait states, every write to the FIFO register pushes four entries. Find the bug.

      Solution

      The condition ignores PENABLE and PREADY, so it is true at the end of every cycle in which PSEL is high: 1 SETUP + 2 wait states + 1 completing cycle = 4 pushes. With zero waits it still pushes twice, but a test that only checks the last value written to a plain register never notices. Writes must happen only on the completing edge:

      Lesson for the testbench: randomise wait states from day one, or this class of bug stays hidden.

      E7

      Cycle counting

      Basic

      Eight back-to-back transfers have wait states [0, 1, 0, 2, 0, 0, 3, 0]. How many PCLK cycles do they take, and what fraction of cycles complete a transfer?

      Solution

      Each transfer is 2 + waits cycles: 8 × 2 + (0+1+0+2+0+0+3+0) = 16 + 6 = 22 cycles. Eight completions in 22 cycles is about 36%, against the zero-wait best case of 50%.

      E8

      Debug this driver

      Advanced

      Find every problem in this driver task.

      Solution
      • No loop on PREADY: it leaves ACCESS after one cycle, breaking WAIT_HOLD with any completer that inserts waits, and samples PRDATA before it is valid.
      • Blocking assignments straight to the interface at the clock edge race with the DUT. Use a clocking block and <=.
      • PSEL is always dropped, so back-to-back transfers are never generated.
      • PSTRB and PPROT are never driven (X on an APB4 bus), and PSLVERR is never captured.

      Compare with apb_master_driver in chapter 12.

      E9

      Assert the PWAKEUP recommendation

      Advanced

      For APB5, write a warning-level property that PWAKEUP is high in every cycle where PSEL is high, and a cover property for PWAKEUP leading PSEL by at least two cycles.

      Solution
      E10

      APB4 requester, APB3 completer

      Advanced

      You are designing the adapter between an APB4 requester and an APB3 completer. What do you do with a write where PSTRB is not all ones? Give two options and their costs, and the test you would write for each.

      Discussion
      • Reject: answer with PSLVERR without forwarding the write. Cheap and safe; software must avoid sub-word writes to that completer. Test: partial write returns error and the register is unchanged.
      • Read-modify-write: read the word, merge the strobed bytes, write it back. Transparent to software, but two transfers, not atomic, and wrong for registers with read side effects. Test: partial writes preserve the other bytes; read-to-clear registers are excluded.
      • Passing it through unchanged is the bug from chapter 05's interop trap.
      15 · QUIZ

      Test yourself

      26 questions from signal basics to SVA and testbench design, in random order. Each answer comes with an explanation. Your best score on a full set of ten or more is kept in this browser.

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      FAQ

      APB protocol: common questions

      Quick answers to what people most often ask about AMBA APB and how to verify it. Each answer links to the part of the lab that shows it on a waveform.

      What is the AMBA APB protocol?

      APB (Advanced Peripheral Bus) is the simplest bus in Arm's AMBA family. It connects low-bandwidth peripherals, such as timers, UARTs, GPIO and configuration registers, to the rest of a chip. APB is not pipelined: every transfer takes at least two clock cycles, a SETUP cycle and an ACCESS cycle. It usually sits behind a bridge from a faster bus such as AHB or AXI. Start with the basics →

      What are the APB signals?

      Every version has PCLK, PRESETn, PSELx, PENABLE, PADDR, PWRITE, PWDATA and PRDATA. APB3 adds PREADY and PSLVERR. APB4 adds PPROT and PSTRB. APB5 adds PWAKEUP, the user signals (PAUSER, PWUSER, PRUSER, PBUSER) and optional parity check signals. See every signal →

      What are the states of the APB state machine?

      IDLE, SETUP and ACCESS. In SETUP, PSEL is high and PENABLE is low, and SETUP always lasts exactly one cycle. In ACCESS, PSEL and PENABLE are both high. The transfer completes on the rising edge where PSEL, PENABLE and PREADY are all high. The bus then returns to IDLE, or goes straight to SETUP if another transfer is pending. Explore the state machine →

      What is a wait state in APB?

      A completer that needs more time holds PREADY low during ACCESS. Each cycle with PREADY low is a wait state. During wait states the requester must keep PSEL, PENABLE, PADDR, PWRITE and PWDATA stable, and also PSTRB and PPROT from APB4 onward. Wait states exist from APB3 onward, because APB2 has no PREADY. Watch a write with two wait states →

      When is PSLVERR valid?

      Only in the last cycle of a transfer, when PSEL, PENABLE and PREADY are all high. Outside that cycle it is not sampled, and Arm recommends, but does not require, driving it low. An error on a read means PRDATA may not be valid. An error on a write does not guarantee that the peripheral's register was left unchanged. Watch an error response →

      Can PADDR change during a wait state?

      No. From SETUP until the transfer completes, the requester must hold the address, control and write data stable. A moving address is a classic bug: the completer samples PADDR at the completing edge, so the write lands at the wrong address. An SVA check with $stable catches it. Insert this bug and catch it →

      What is the difference between APB2, APB3, APB4 and APB5?

      APB2 (AMBA 2) has a fixed two-cycle transfer, with no wait states and no error response. APB3 adds PREADY for wait states and PSLVERR for errors. APB4 adds PPROT for protection attributes and PSTRB for byte-level writes. APB5 adds PWAKEUP, user sideband signals and optional parity protection. Compare the versions →

      What is the difference between APB and AHB?

      AHB is a pipelined, higher-performance bus with burst transfers, used for memories and fast components. APB is non-pipelined and much simpler, which keeps peripherals small and low-power. A typical chip connects its APB peripherals through an AHB-to-APB or AXI-to-APB bridge.

      What does PSTRB do in APB4?

      PSTRB has one bit per byte lane of PWDATA. On a write, only the byte lanes whose strobe bit is high are updated. On a read, the requester must drive all PSTRB bits low. Watch a partial write →

      Is PREADY sampled in the SETUP phase?

      No. PREADY only matters in ACCESS. A completer may drive it high early, but the transfer cannot complete before the ACCESS cycle, so every transfer still takes at least two cycles. Watch an early PREADY →

      How do you verify an APB interface?

      Usually with three things. An SVA protocol checker enforces the timing rules, such as stable signals during wait states and SETUP always followed by ACCESS. Constrained-random stimulus varies wait states, errors, strobes and back-to-back transfers. Functional coverage proves those cases were actually hit. In UVM, this lives in an APB agent (driver, monitor and sequencer) plus a scoreboard. See the reference testbench →

      Which assertions should an APB protocol checker have?

      At minimum: no PENABLE without PSEL; PENABLE only rises right after a SETUP cycle; SETUP is always followed by ACCESS to the same peripheral; address, control and write data stay stable until the transfer ends; PENABLE goes low after every completed transfer; reads never carry byte strobes; PSLVERR is only high in the completing cycle; and control signals never carry X or Z while selected. Try all 19 assertions →